This invention relates generally to the semiconductor devices, and more particularly to lead frames used in the assembly of micro electronic devices.
Integrated circuit devices, having an integrated circuit chip and a lead frame which are sealed within a protective enclosure find wide use in products, among which are consumer electronics, computers, automobiles, telecommunications and military applications. A means to electrically interconnect an integrated circuit chip to circuitry external to the device frequently takes the form of a lead frame. The lead frame is formed from a highly electrically and thermally conductive material, such as copper or copper alloys. The lead frame is stamped or etched into a plurality of leads, and a central area, called a chip mount pad, onto which the integrated circuit chip is attached. The chip is electrically connected to the leads, usually by wire bonding, and the device is encapsulated to provide mechanical and environmental protection.
Conventional lead frames, as illustrated in a plan view in FIG. 1, are assembled into a plastic encapsulated semiconductor package. The lead frame includes a planar chip mount pad 110 somewhat larger than the integrated circuit chip to be assembled, as indicated by dashed lines 120. The chip is to be affixed by an adhesive or an alloy to the mount pad 110, and is connected to the inner portions of the leads by bonding wires, prior to encasing in a plastic resin.
Lead frames are fabricated by stamping or etching relatively thin strips of metal to form a plurality of lead frames attached to a system of support rails 130 which provide a means for transporting through semiconductor packaging assembly equipment. In an as fabricated lead frame strips, the leads 112 are maintained in the plane of the support rails 130. The centrally located chip mount pad 110 is attached to the support rails by narrow tie straps 113. The chip mount pad 110 and the innermost portion of the tie straps 113 are downset or Z-axis offset from the plane of the support rails 130 in order to allow the surface of a chip 120 to be more nearly in the plane of the lead tips, thereby requiring shorter wire bonds 125 and allowing a more reliable bonding process.
Currently many lead frames are fabricated with a single or multiple small circular mount pads 202 as shown in FIG. 2, or simply have tie straps to which the chip is attached, and the large chip pad is eliminated. The small chip pads 202 are connected to outer support rails 205 by thin etched or stamped tie straps 206. Support rails 205 also hold together one or more lead frames in a strip until assembly of the package is completed.
Those lead frames having one or more small pads 202 as in FIG. 2 are typically referred to as S-pad or small pad lead frames. A small, circular pad is positioned approximately mid-way from the edge of the tie strap 206 to the center of the lead frame where the tie straps intersect 208. The chip, represented by dashed lines 203 is positioned atop the pads 202 and the unpatterned surface of the chip affixed to the pads by a chip attach adhesive (not shown). As with conventional lead frames, the tie straps and mount pads are offset from the plane of the support rails in order to provide a more planar structure with reduced bond wire lengths.
Lead frames having a reduced chip pad area were developed in response to a failure mechanism in surface mount plastic packages, often referred to as xe2x80x9cpop corn effectxe2x80x9d or vapor pressure package cracking, and which is illustrated in FIG. 3. With conventional lead frames, ambient moisture ingress into the plastic resin is trapped between the solid chip 310 with mount pad 320 and the resin 340. When subjected to a rapid thermal excursion, such as solder attachment to a printed wiring board, vapor pressure within the package causes areas of the weak adhesion in the adhesive 311 between the chip 320 and chip mount pad 310, and between the pad 310 and the resin 340 to delaminate. Arrows 350 represent areas where vapor pressure builds up, and which in turn result in delamination 351, and often in bulges and cracks 352 in the resin. This failure mechanism is associated with large semiconductor die and is most prominent with thin packages.
xe2x80x9cSxe2x80x9d pad or small chip contact pads in the lead frames solve the failure by eliminating large planar surfaces between the chip pad and resin. Further, they greatly reduce the amount of chip attach adhesive used and which has been found to be both a source of vapor pressure, as well as the material within the system having poor mechanical strength.
However, a severe limitation of S-pad lead frames is a loss of thermal dissipation found in conventional lead frames having thermally conductive chip mount pads equal to or greater in area than the chip itself. As illustrated in FIG. 4, heat transfer paths from a semiconductor device 420 are (1) into the metal chip pad 410, (2) from the pad through the resin 440 to the back of the package, (3) from the pad into the leads with direct transfer to an external printed circuit board 460, (4) from the surface of the chip through the resin 440 into the ambient, and (5) from the chip through the resin to the leads 412. In effect, large chip mount pads 410 are used as heat spreaders within the package by expanding the area of the heat dissipation, and by bringing the pad into close proximity to the leads.
A second issue with S-pad lead frames, not present with conventional chip mount pad lead frames is a tendency for warping and bowing of the narrow tie straps, and consequently non-planar mount pads which in turn result in yield and reliability losses.
In the lead frame manufacturing process, patterned lead frame strips are positioned in a die and the chip pads are formed downward or xe2x80x9czxe2x80x9d axis offset using a tool which elongates that portion of metal under pressure, repositioning the integrated patterned tie straps and chip pad. Under pressure the ductile metal in two or more tie straps is forced downward to form angled bends and is pressed toward the center of the lead frame by using a forming punch to press the tie straps against the die surface. The ductile metal converges toward the center and often warps or bows in S-pad lead frames. With conventional leaf frames, the large die pad area allows the stress to be relieved in the pad itself, and consequently has little tendency to warp.
As smaller and thinner integrated circuit packages, having good reliability with respect to both moisture ingress and thermal dissipation are demanded by the industry, lead frames which support these issues are needed.
Clearly, it would be very desirable for the industry to have a lead frame with the mechanical stability and thermal transport advantages of conventional chip pads larger than the chip perimeter, but with the advantages of S-pads having small contact areas to the chip, and which use a very small amount of chip attach adhesive, known to contribute to vapor phase package cracking.
It is an object of this invention to provide a semiconductor device with a lead frame having a chip mount pad including small contact areas, as well as the thermal transport advantages of a large mount pads.
It is an objective to provide a device which provides improved package reliability during solder reflow processing.
It is an object of the invention to provide a semiconductor package which requires a minimal amount of chip attach adhesive, supporting both reduced cost and improved reliability of the product.
It is further an object of the invention to provide a lead frame which is compatible with multiple semiconductor chip sizes and shapes, thereby minimizing chip specific tooling inventory and manufacturing costs of customized chip mount pads.
It is an object of the invention to provide a lead frame chip pad which acts like a heat spreader within the semiconductor package.
It is further an object of the current invention to provide a method for manufacturing a lead frame having small pad contact area to the chip, and yet large pad thermal dissipation advantages.
It is further an object of the invention to provide a lead frame having small contact areas to the chip, but the mechanical stability of conventional large mount pads.
Yet another advantage of the current invention is to provide a lead frame having the advantages of high thermal conductivity, the manufacturing advantages of ductility, and the stress relief of a large area chip pad.
The present invention is a semiconductor device which comprises a lead frame that includes a large area mount pad having small elevated pads. A semiconductor chip is attached to the elevated pads using the minimum amount of chip attach adhesive which is known to contribute to vapor pressure package cracking. The large area pad allows good thermal spreading and dissipation of heat through the encapsulated package.
Owing to the reduced area for chip attachment, the lead frame is usable for a family of semiconductor chips of varying sizes and shapes; this in turn reduces the number of device specific lead frames to be tooled and to be held in inventory.
Alloys of copper are the heavily favored lead frame materials because of their excellent thermal conductivity, their ease of processing, and the malleability and ductility of these copper alloys allows greater latitude in forming lead frame variations. Moreover, the large area chip pad provides stress relief during the lead frame manufacturing process, which eliminates the warpage and distortion that frequently occurs with small pad lead frames.